Array read access control using MUX select signal gating of the read port

ABSTRACT

An apparatus, a method, and a computer program product are provided for time reduction for an array read access control consisting of a bitcell with logic gating and a pull down device included, therein. To reduce gate delay this design implements gating logic inside the bitcell. The multiplex select gating signals are brought into the bitcell, and are gated with the data array. The gating logic controls the pull down device, and MUX select signals can be produced as a readout of the bitcell. This design reduces gate delay because the dependency upon the gating logic is overridden and the number of stages is reduced.

FIELD OF THE INVENTION

The present invention relates generally to array read access control,and more particularly, to array read access consisting of bitcells withgating logic included that are designed to reduce gate delay whenproducing MUX select signals.

DESCRIPTION OF THE RELATED ART

Standard bitcells and array read access controls are used in dataprocessing systems to perform the function of accepting written data,storing this data in arrays, reading this data and then transforming thedata into decoded select signals. Usually, these devices consist of aconventional bitcell with a read port followed by specific gating logicto produce the desired MUX select signals. After a write is performedand stored as data in an array, the bitcell will produce a readout thatwill be gated to produce the MUX select signals. A read of the dataarray must be completed before the bitcell readout can be gated outsideof the bitcell. Any operation that is based upon the read result fromthe bitcell will require additional cycles, which increases the timedelay of the circuit.

Referring to FIG. 1 of the drawings, the reference numeral 100schematically depicts a conventional bitcell with a read port. The writewordline 105, is connected to the gates of two nFET transistors 120 and125. The write bitline 110 is connected to the source of nFET 120. Thedrain of nFET 120 is connected through junction 130 to an inverter 135.The output of inverter 135 is connected to junction 140, which isconnected to the source of nFET 125. The complement of the write bitline115 exists at the drain of nFET 125. At junction 140, another inverter145 is connected with its output attached to junction 130. The two nFETtransistors 120 and 125, and the two inverters in series 135 and 145,create a static memory cell 150, which maintains a constant value in thebitcell. When the write wordline 105 is on, the values on the writebitlines 110 and 115 will be passed to memory cell 150, and the memorycell 150 will hold new values at junctions 130 and 140. Junction 140 isalso connected to the gate of nFET transistor 155.

The drain of nFET 155 is connected to the source of nFET transistor 170.The read wordline 160 is connected to the gate of nFET 170. A read willoccur when the read wordline 160 is activated. The bitcell value willdetermine the value of the read. The drain of nFET 170 is the readbitline 165. The nFET transistors 170 and 155 make up the pull downdevice 175, and both transistors must be activated before the readbitline 165 will be pulled down. The pull down device 175 initiates theread. If nFET 155 is activated, the read bitline 165 will pull down. IfnFET 155 is not activated, then the read bitline 165 will maintain itsprecharged state. The source of nFET 155 is connected to ground 180. Thepull down device 175 allows the signal that has been read to be pulleddown as a readout of the read bitline 165. At this point the readout canbe gated to produce the MUX select signals.

Referring to FIG. 2 of the drawings, the reference numeral 200illustrates a block diagram depicting a conventional array read accesscontrol comprising a readout of a standard bitcell followed by signalgating. The bitcell 208 corresponds to FIG. 1, reference numeral 100.The Array Bit Slice 205 depicts an array of these conventional bitcells208, as they would exist in a processor. The readout 210 corresponds tothe read bitline 165 in FIG. 1. This readout signal 210 is produced by aconventional bitcell with a read port. The readout 210 is then connectedto the specific gating logic 220 as an input. The multiplex gatingsignals 215 are also connected to the gating logic 220 as the otherinput. The MUX select signals 225 are the decoded signals produced bythe gating logic 220. This diagram shows that a conventional array readinvolves two separate steps to produce the desired select signals. Thebitcell provides the data which will be read out of the array. The readwordline 160 (FIG. 1) will activate the read, and the value of the readwill determine whether the read bitline 165 (FIG. 1) gets pulled down orremains precharged. After this step the readout signals 210 and thegating signals 215 are gated to produce the MUX select signals.

These separate steps lead to a time delay that was previously described.Any operation that requires a readout signal from the bitcell willrequire additional clock cycles. Additional delay in this process causesthe array read timing operation to become more critical. This resultforces the array read devices to be designed with timing constraints asthe primary issue. If timing issues are less significant, then arrayread devices can be designed to be smaller in area, more reliable and/ormore power efficient. Therefore, there is a need to reduce the timedelay involved with conventional array read access controls.

SUMMARY OF THE INVENTION

The present invention provides a method, an apparatus, and a computerprogram for the reduction of time delay for array read access controlsconsisting of a bitcell with gating logic and a pull down deviceincluded, therein. Gating logic is brought into the bitcell, whichallows for a reduction in gate delay. Because the gating of the dataarray can be accomplished before a complete read of the data array, thenumber of stages is reduced. The multiplex select gating signals arebrought into the bitcell and gated with the data array. This allows thegating logic to control the pull down device, and the readout of thebitcell is no longer required to be gated. As a result of this timedelay reduction, the array read timing operation becomes less criticaland the devices may be sized to achieve greater reliability and/or lowerpower consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 schematically depicts a conventional bitcell with a read port;

FIG. 2 is a block diagram depicting a conventional array read accesscontrol;

FIG. 3 schematically depicts a modified bitcell with a read port and thenecessary gating logic included;

FIG. 4 is a block diagram depicting a modified array read access controlwithout the gating logic outside of the bitcell; and

FIG. 5 is a flow chart depicting the array read process inside themodified bitcell.

DETAILED DESCRIPTION

In the following discussion, numerous specific details are set forth toprovide a thorough understanding of the present invention. However,those skilled in the art will appreciate that the present invention maybe practiced without such specific details. In other instances,well-known elements have been illustrated in schematic or block diagramform in order not to obscure the present invention in unnecessarydetail. Additionally, for the most part, details concerning networkcommunications, electromagnetic signaling techniques, and the like, havebeen omitted inasmuch as such details are not considered necessary toobtain a complete understanding of the present invention, and areconsidered to be within the understanding of persons of ordinary skillin the relevant art.

Referring to FIG. 3 of the drawings, the reference numeral 300 generallydesignates a modified bitcell with a read port and the necessary gatinglogic included. The write wordline 305, is connected to the gate of twonFET transistors 320 and 325. The write bitline 310 is connected to thesource of nFET 320. The drain of nFET 320 is connected through junction330 to an inverter 335. The output of inverter 335 is connected tojunction 340, which is connected to the source of nFET 325. Thecomplement of the write bitline 315 exists at the drain of nFET 325. Atjunction 340, another inverter 345 is connected with its output attachedto junction 330. The two nFET transistors 320 and 325, and the twoinverters in series 335 and 345, create a static memory cell 350, whichmaintains a constant value in the bitcell. When the write wordline 305is on, the values on the write bitlines 310 and 315 will be passed tothe memory cell 350, and the memory cell 350 will hold new values atjunctions 330 and 340.

Junction 330 is connected to a NOR gate 370 as an input throughcommunication channel 355. Communication channel 355 can be connected tojunction 330 or 340. Therefore, communication channel 355 can be used tocarry the true bitline signal at junction 330 or the complement bitlinesignal at junction 340. The gating signals 360 provide the other inputfor the NOR gate 370. The output of the NOR gate 370 is connected to thegate of nFET transistor 380. The drain of nFET 380 is connected to thesource of nFET 386. The drain of nFET 386 is the read bitline 384. Thegate of nFET 386 is connected to the read wordline 382. The source ofnFET 380 is connected to ground 390. The pull down device 388 consistsof nFET 380 and nFET 386. The pull down device 388 will pull down theread bitline 384 producing the readout of the bitcell. The activation ofnFETs 380 and 386 is required to pull down the read bitline 384.Therefore, in this design both the gating signals 360 and the junction330 must have the logical value of “0” for the read bitline 384 to bepulled down.

To achieve this result the array data is gated with the gating signals360 (this occurs during the address decode for the read wordline).Essentially, the gating of the array data with the gating signalsproduces a decoded signal before the read is activated. For example, a5:1 multiplexer has four of the five select signals stored in the arrayas 1-hot and the remaining, multiplex select signal, exists outside ofthe array. The values of all five select signals must be 1-hot whencontrolling the multiplexer. Previous methods require an array readfollowed by the gating of the array readout data to insure the 1-hotcondition among all five signals. This modified design brings themultiplex select signal into the bitcell as an input and the gating canbe performed before the read is activated. The multiplex select signalis denoted as gating signals 360. The inclusion of this NOR gate insidethe array bitcell allows for the timing dependency on the gating logicto be overridden and the number of stages reduced. The gating logic iscompletely static. Now, the readout of the array is a fully decodedrepresentation of the stored array data plus the master select signal.This is a clear reduction of gate delay stages in these high frequencyarray reads. A reduction of gate delay stages in high frequency arraydesigns is critical for achieving desired cycle times.

FIG. 3 illustrates a NOR gate 370 as the gating logic used in thisbitcell, but other gating logic may be used. The gating signals 360 inFIG. 3 only provides one input, but more inputs are possible with thecorrect gating logic. In this design the read wordline is a pulsed clocksignal that controls when the pull down device is activated. Only oneclock signal is used for the reading and the pulling down of the bitlineand timing issues are minimal. The activation of the read wordline 382and the write wordline 305 must be mutually exclusive.

Referring to FIG. 4 of the drawings, reference numeral 400 depicts ablock diagram illustrating a modified array read access control with nogating logic following the bitcell readout. The Bitcell with GatingLogic 408 corresponds to reference numeral 300 in FIG. 3. The Array BitSlice 405 denotes an array of bitcells as they would exist in aprocessor. The readout 410 corresponds with the read bitline 384 in FIG.3. The readout of the bitcell 410 is the fully decoded MUX selectsignals 415. As shown in FIG. 4, no gating logic is needed because theMUX select signals 415 are fully decoded by the Bitcell with GatingLogic 408. As a result of this time delay reduction, the array readtiming operation becomes less critical and the devices may be sized toachieve greater reliability and/or lower power consumption.

Referring to FIG. 5 of the drawings, reference numeral 500 depicts aflow chart illustrating the process of an array read in the modifiedbitcell with the gating logic included. The first step 506 of theprocess 500 involves producing the gating signals 360 outside of themodified bitcell 300. The gating signals 360 are then brought into thebitcell in step 508. If the write wordline 305 in the bitcell isactivated, then in step 504 a write is stored as data in an array.Process step 510 denotes that this data array signal 355 is one input ofthe gating logic (NOR gate 370), and process step 512 denotes that thegating signals 360 are the other input of the gating logic. At thisstage, the data array and the gating signals are gated as shown by step514. If the output of the gating logic (NOR gate 370) is a logical “0,”then step 524 denotes that the read bitline 384 remains precharged andis not pulled down. If the output of the gating logic (NOR gate 370) isa logical “1,” then step 518 denotes that the pulldown device 388 isactivated. When the pulldown device 388 is activated, then in step 520the read bitline 384 is pulled down as a decoded readout 410.

It is understood that the present invention can take many forms andembodiments. Accordingly, several variations of the present design maybe made without departing from the scope of the invention. Thecapabilities outlined herein allow for the possibility of a variety ofprogramming models. This disclosure should not be read as preferring anyparticular programming model, but is instead directed to the underlyingconcepts on which these programming models can be built.

Having thus described the present invention by reference to certain ofits preferred embodiments, it is noted that the embodiments disclosedare illustrative rather than limiting in nature and that a wide range ofvariations, modifications, changes, and substitutions are contemplatedin the foregoing disclosure and, in some instances, some features of thepresent invention may be employed without a corresponding use of theother features. Many such variations and modifications may be considereddesirable by those skilled in the art based upon a review of theforegoing description of preferred embodiments. Accordingly, it isappropriate that the appended claims be construed broadly and in amanner consistent with the scope of the invention.

1. An apparatus controlling array read access for use with an arraybitcell having a true and complement signal, a multiplex select gatingsignal, and a read wordline, comprising: a logic circuit that is atleast configured to receive the multiplex select gating signal, and thetrue and complement signals; a pull down device that is at leastconfigured to receive the read wordline signal; and output signal meansinterconnecting the logic circuit and the pull down device for gatingthe read wordline signal as a function of the gating signal.
 2. Theapparatus of claim 1, wherein the bitcell is at least configured tohouse the logic circuit and the pull down device.
 3. The apparatus ofclaim 2, wherein the logic circuit is at least configured to receive thetrue signal or the complement signal as an input.
 4. The apparatus ofclaim 3, wherein the logic circuit further comprises a NOR gate that isat least configured to receive the true signal or the complement signaland the multiplex select gating signal, and produce a time delayedoutput signal.
 5. The apparatus of claim 2, wherein the pull down deviceis at least configured to receive a read wordline signal and the timedelayed output signal, and pull down a readout signal.
 6. The apparatusof claim 5, wherein the read wordline signal is a pulsed clock signalthat is at least configured to activate the pull down device.
 7. Theapparatus of claim 1, wherein the output signal means further comprisesat least configuring the logic circuit to control the pull down device.8. A method for reducing the time delay for array read access controlfor use with an array bitcell having a true and complement signal, aread wordline signal, and a pull down device, comprising: bringing amultiplex select gating signal inside the bitcell; implementing a logiccircuit inside the bitcell to receive the multiplex select gating signaland the true and complement signal; connecting the logic circuit and thepull down device; and pulling down a readout signal.
 9. The method ofclaim 8, wherein the step of implementing a logic circuit inside thebitcell to receive the multiplex select gating signal and the true andcomplement signal further comprises implementing the logic circuit,wherein the logic circuit can receive the true signal or the complementsignal.
 10. The method of claim 9, wherein the step of implementing thelogic circuit further comprises configuring a NOR gate, wherein the NORgate receives the multiplex select gating signal and the true signal orthe complement signal as inputs.
 11. The method of claim 8, wherein thestep of connecting the logic circuit and the pull down device furthercomprises feeding the output of the logic circuit into the pull downdevice.
 12. The method of claim 11, wherein the step of feeding theoutput of the logic circuit into the pull down device further comprisesconfiguring the pull down device, wherein the read wordline signal is afunction of the multiplex select gating signal.
 13. The method of claim8, wherein the step of pulling down the readout signal further comprisesconfiguring the logic circuit and the pull down device, wherein thelogic circuit controls the pulling down of the readout signal.
 14. Acomputer program product for reducing the time delay for array readaccess control for use with an array bitcell having a true andcomplement signal, a read wordline signal, and a pull down device, withthe computer program product having a medium with a computer programembodied thereon, wherein the computer program comprises: computer codefor bringing a multiplex select gating signal inside the bitcell;computer code for implementing a logic circuit inside the bitcell toreceive the multiplex select gating signal and the true and complementsignal; computer code for connecting the logic circuit and the pull downdevice; and computer code for pulling down a readout signal.
 15. Thecomputer program product of claim 14, wherein the computer code forimplementing a logic circuit inside the bitcell to receive the multiplexselect gating signal and the true and complement signal furthercomprises implementing the logic circuit, wherein the logic circuit canreceive the true signal or the complement signal.
 16. The computerprogram product of claim 15, wherein the computer code for implementingthe logic circuit further comprises configuring a NOR gate, wherein theNOR gate receives the multiplex select gating signal and the true signalor the complement signal as inputs.
 17. The computer program product ofclaim 14, wherein the computer code for connecting the logic circuit andthe pull down device further comprises feeding the output of the logiccircuit into the pull down device.
 18. The computer program product ofclaim 17, wherein the computer code for feeding the output of the logiccircuit into the pull down device further comprises configuring the pulldown device, wherein the read wordline signal is a function of themultiplex select gating signal.
 19. The computer program product ofclaim 14, wherein the computer code for pulling down the readout signalfurther comprises configuring the logic circuit and the pull downdevice, wherein the logic circuit controls the pulling down of thereadout signal.